exemple de code VHDL: un filtre FIR
Voici un exemple de code VHDL pour constituer un filtre FIR. C'est un TP d'initiation au traitement du signal, à l'utilisation des FPGA qui permet d'introduire les notions de "generic" et de "generate".
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-- Ludovic Barrandon - 2005 --
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
package firn_cte_pack is
constant Wdata : integer := 8; -- taille des données à traiter dans le filtre
constant N : integer := 4; -- taille des données à traiter dans le filtre
TYPE connect IS ARRAY (0 TO N-1) OF std_logic_vector(Wdata-1 DOWNTO 0);
constant coef_fir : connect := ("10000000","01111111","01111111","10000000");
end firn_cte_pack;
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-- Ludovic Barrandon - 2005 --
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-- PACKAGE CORRESPONDANT AU fir
-- direct 'fir0_fir_direct.vhd'
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package fir_cte_pack is
constant Wdata : integer := 8; -- taille des données à traiter dans le filtre
constant coef_init : std_logic_vector(Wdata-1 DOWNTO 0) := "01111111";
end fir_cte_pack;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use WORK.firn_cte_pack.all;
ENTITY FIRn_TB IS
END FIRn_TB;
ARCHITECTURE behavior OF FIRn_TB IS
COMPONENT FIRn
GENERIC(
c_init : connect := coef_fir
);
PORT(
CLK : IN std_logic;
EN : IN std_logic;
entree : IN std_logic_vector(Wdata-1 downto 0);
sortie : OUT std_logic_vector(Wdata-1 downto 0)
);
END COMPONENT;
signal CLK : std_logic := '0';
signal EN : std_logic := '1';
signal entree : std_logic_vector(Wdata-1 downto 0) := (others => '0');
--Outputs
signal sortie : std_logic_vector(Wdata-1 downto 0);
constant period : time := 10 ns;
BEGIN
ut: FIRn
GENERIC MAP(
c_init => coef_fir
)
PORT MAP (
CLK => CLK,
EN => EN,
entree => entree,
sortie => sortie
);
pclk :process
begin
clk <= '0';
wait for period/2;
clk <= '1';
wait for period/2;
end process pclk;
stim: process
begin
-- à compléter
END LOOP;
end process stim;
END;
------------------------------
-- Ludovic Barrandon - 2005 --
------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use WORK.fir_cte_pack.all;
ENTITY FIR1 IS
GENERIC(
c_init : std_logic_vector(Wdata-1 DOWNTO 0) := coef_init
);
PORT(
CLK : IN std_logic;
EN : IN std_logic;
entree : IN std_logic_vector(Wdata-1 DOWNTO 0);
bloc_prec : IN std_logic_vector(Wdata-1 DOWNTO 0);
sortie : OUT std_logic_vector(Wdata-1 DOWNTO 0)
);
END;
architecture TP of FIR1 is
CONSTANT zeros : std_logic_vector(Wdata-1 DOWNTO 0) := (others => '0');
BEGIN
gmx : PROCESS(clk , en)
VARIABLE var_sortie : std_logic_vector(2*Wdata-1 DOWNTO 0) := (others => '0');
VARIABLE var_mult : std_logic_vector(2*Wdata-1 DOWNTO 0) := (others => '0');
VARIABLE var_prec : std_logic_vector(2*Wdata-1 DOWNTO 0) := (others => '0');
BEGIN
IF rising_edge(clk) THEN
IF en = '1' THEN
var_mult := entree * c_init;
var_prec := bloc_prec & zeros;
var_sortie := var_mult+var_prec;
sortie <= var_sortie(2*Wdata-1 DOWNTO Wdata);
ELSE
sortie <= (others => '0');
END IF;
END IF;
END PROCESS gmx;
end TP;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use WORK.firn_cte_pack.all;
entity FIRn is
GENERIC(
c_init : connect := coef_fir
);
PORT(
CLK : IN std_logic;
EN : IN std_logic;
entree : IN std_logic_vector(Wdata-1 DOWNTO 0);
sortie : OUT std_logic_vector(Wdata-1 DOWNTO 0)
);
end FIRn;
architecture a_generate of FIRn is
SIGNAL -- compléter
COMPONENT FIR1
GENERIC(
c_init : std_logic_vector(Wdata-1 DOWNTO 0)
);
PORT(
CLK : IN std_logic;
EN : IN std_logic;
entree : IN std_logic_vector(7 downto 0);
bloc_prec : IN std_logic_vector(7 downto 0);
sortie : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
begin
gFIR : for i in 0 to N-1 generate
BEGIN
Inst_FIR1: FIR1
GENERIC MAP(
-- compléter
)
PORT MAP(
CLK => ,
EN => ,
entree => ,
bloc_prec => ,
sortie =>
);
end generate;
----------------
-- compléter
end a_generate;